1. Field
Aspects of the present disclosure relate to semiconductor devices, and more particularly to complementary strain materials in field effect transistor (FET) structures using fin (FinFET) channels.
2. Background
Strain engineering for FET performance has been viewed as an alternative to reducing gate oxide thickness. In standard FET geometries, imparting a strain in semiconductor chip regions, such as the source and drain regions of a FET, is an approach employed in the related art. In FinFET structures, however, the volume of the fin available for strain engineering is small. In addition, the compressive strain along the channel direction that is beneficial for p-channel (e.g., hole charge carriers) FinFETs is detrimental to the n-channel (e.g., electron charge carriers) FinFETs. The volume and compressive strain issues have limited the ability to apply strain engineering in FinFET devices.